Conventionally, various insulating films, such as a silicon oxide (SiO2) film, a silicon nitride (SiNx) film, and a silicon oxynitride (SiON) film, which are formed by a Plasma Enhanced Chemical Vapor Deposition Method (hereinafter referred to as a “plasma CVD method”), and a multilayer insulating film in which the above-mentioned films are appropriately combined and laminated, have been used as a gate insulating film of a thin film transistor (hereinafter referred to as a “TFT”) having a bottom-gate structure.
Japanese Patent Application Laid-Open Publication 2008-177419 describes configurations of a TFT having the bottom-gate structure in which the gate insulating film is made of a silicon oxide film alone and in which the gate insulating film is made of a silicon nitride film alone, for example. Japanese Patent Application Laid-Open Publication H8-97432 describes a TFT having the bottom-gate structure in which the gate insulating film is made of a multilayer insulating film that is formed by laminating a silicon oxide film on a silicon nitride film by the plasma CVD method.